Recently, integrated circuit devices have become more highly integrated. To provide highly integrated circuit devices, the dimensions of the integrated circuit devices, for example, field effect transistors (FETs), have been reduced. For example, a channel length of a FET has generally been shortened from about 20 to about 30 nm. Once the size of these devices has been reduced, it may be difficult to control the influence of drain potential on source and channel potentials due to a short channel effect.
Conventional, complementary metal oxide semiconductor (CMOS) transistors have horizontal channels, i.e. have channels that are parallel to a surface of an integrated circuit substrate. Devices having horizontal channels may have a structural disadvantage when the dimensions of the device are reduced, for example, an increased occurrence of the short channel effect.
To address the issue with respect to CMOS transistors, a double gate FET has been proposed to control a channel potential. In particular, channel potential may be controlled by arranging gates on both sides of the channel. Furthermore, Fin Field Effect Transistors (Fin-FETs), such as those disclosed in U.S. Pat. No. 6,413,802 B1, entitled Fin-FET Transistor Structures Having a Double Gate Channel Extending Vertically From a Substrate and Methods of Manufacture to Chenming Hu et al., in which double gates are provided on the sides of the channel to provide an enhanced drive current and reduce the likelihood of the occurrence of the short channel effect. Furthermore, the double gate Fin-FET device includes a vertical channel, unlike conventional CMOS transistors including the horizontal channel and, thus, may provide advantages over the horizontal channel device. In particular, vertical channel structures may be smaller relative to horizontal devices and may be highly compatible with methods of fabricating conventional CMOS transistors having horizontal channels.
Methods of fabricating integrated circuit devices having three dimensional channels on an integrated circuit substrate may include a photolithography process. However, the extent to which a line width may be reduced using a photolithography process may be limited. Thus, methods providing a spacer in the process of forming the three dimensional channel have been developed.
Referring now to FIGS. 1A through 4C, conventional methods of fabricating MOS transistors will be discussed. FIGS. 1A through 4A are top views illustrating processing steps in the fabrication of conventional metal oxide semiconductor (MOS) transistors. FIGS. 1B through 4B are cross-sectional views taken along the line A-A′ of FIGS. 1A through 4A, respectively, illustrating processing steps in the fabrication of conventional MOS transistors. FIGS. 1C through 4C are cross-sectional views taken along the line B-B′ of FIGS. 1A through 4A, respectively, illustrating processing steps in the fabrication of conventional MOS transistors.
As illustrated in FIGS. 1A through 1C, a mask pattern M is formed on an active region of an integrated circuit substrate 10. Subsequently, the integrated circuit substrate 10 is etched using the mask pattern M as an etch mask to form a trench around the active region. An insulating layer is formed on the integrated circuit substrate 10. In the trench, the insulating layer is removed to expose the mask pattern M forming an isolation layer 11 in the trench. As illustrated in FIGS. 2A through 2C, the mask pattern M is removed to expose a surface of the integrated circuit substrate 10 and sidewalls of the isolation layer 11. The active region has a length of ‘L1’ and a width of ‘W1’ as illustrated in FIG. 2A.
Referring now to FIGS. 3A through 3C, a spacer 13 is formed on the sidewalls of the exposed isolation layer 11 where the mask has been removed. The integrated circuit substrate 10 is etched to form a trench 14 in the integrated circuit substrate 10 using the isolation layer 11 and the spacer 13 as an etch mask. As illustrated in FIGS. 4A through 4C, the spacer 13 is removed to expose the integrated circuit substrate 10 and a portion of the isolation layer 11 is also removed. As illustrated in FIG. 4C, portions of the integrated circuit substrate 10 protrude from a surface of the isolation layer 11. The protruded portions define channel regions C that are parallel to each other.
As discussed above, conventional methods of fabricating integrated circuit devices may form a trench 14 using a spacer 13 positioned on an edge of the active region. Thus, an area of the active region may be reduced in proportion to a width of the spacer. In other words, as illustrated in FIGS. 2A and 4A, in the active region, the length ‘L1’ and the width ‘W1’ of the active region (FIG. 2A) may be reduced to a length of ‘L2’ and a width of ‘W2’ (FIG. 3A) after the spacer is formed. Accordingly, improved methods of fabricating integrated circuit devices may be desired.